`timescale 1ns / 1ns

module led_sim();

reg sys_clk;
reg reset;
reg fifo_empty;
reg usb_rstn;
wire led_red;
wire led_green;
wire led_blue;

led_driver u_led_dut
(
    .sys_clk    (sys_clk),
    .reset      (reset),

    .fifo_empty (fifo_empty),
    .usb_rstn   (usb_rstn),

    .led_red    (led_red),
    .led_green  (led_green),
    .led_blue   (led_blue)
);

defparam u_led_dut.SYS_FREQ = 'd3072000;
defparam u_led_dut.BREATH_FREQ = 'd10;

always #2 sys_clk <= ~sys_clk;

initial begin
    #0  begin sys_clk <= 0; reset <= 1; usb_rstn <= 0; fifo_empty <= 1;end
    #50 begin reset <= 0; usb_rstn <= 1;end
    #150 begin fifo_empty <= 0; end
    #10000000 $finish();
end

initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, led_sim);    //tb模块名称
end


endmodule


